Method for tuning the threshold voltage of a metal gate and high-k device
US7754594B1 · kind B1 · utility
16Cited by
1References
23Claims
0Family size
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Key dates
| Filing date | Jan 26, 2009 |
| Grant date | Jul 13, 2010 |
| Priority date | — |
| Expiry date | Jan 26, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metal gate and high-k dielectric device includes a substrate, an interfacial layer on top of the substrate, a high-k dielectric layer on top of the interfacial layer, a metal film on top of the high-k dielectric layer, a cap layer on top of the metal film and a metal gate layer on top of the cap layer. The thickness of the metal film and the thickness of the cap layer are tuned such that a target concentration of a cap layer material is present at an interface of the metal film and the high-k dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.