Patent · US Active

Integrated circuit including parylene material layer

US7759792B2 · kind B2 · utility

0Cited by

8References

10Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thorsten Meyer · Regensburg, DE
Markus Brunnbauer · Lappersdorf, DE
Stephan Bradl · Regensburg, DE

Key dates

Filing date	Aug 15, 2007
Grant date	Jul 20, 2010
Priority date	—
Expiry date	Nov 7, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/14
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit includes a substrate including a contact pad, a redistribution line coupled to the contact pad, and a dielectric material layer between the substrate and the redistribution line. The integrated circuit includes a solder ball coupled to the redistribution line and a parylene material layer sealing the dielectric material layer and the redistribution line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.