Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same

US7800182B2 · kind B2 · utility

Assignees

• Infineon Technologies AG · DE
• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Jin-Ping Han · Fishkill, US
• Alois Gutmann · Poughkeepsie, US
• Roman Knoefler · Villach, AT
• Jiang Yan · Beijing, CN
• Chris Stapelmann · Portland, US
• Jingyu Lian · Plattekill, US
• Yung Fu Chong · Singapore, SG

Key dates

• Filing date: Nov 20, 2006
• Grant date: Sep 21, 2010
• Expiry date: May 20, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002

Abstract

In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.