Patent · US Active

Integrated circuit including an array of memory cells and method

US7804708B2 · kind B2 · utility

1Cited by

0References

6Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Ulrike Gruening-von Schwerin · Munich, DE
Lothar Risch · Neubiberg, DE
Peter Baars · Dresden, DE
Klaus Muemmler · Dresden, DE
Stefan Tegen · Dresden, DE
Thomas Happ · Tarrytown, US

Key dates

Filing date	Jul 30, 2008
Grant date	Sep 28, 2010
Priority date	—
Expiry date	Jan 5, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG11C2213/72
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.