Methods of combinatorial processing for screening multiple samples on a semiconductor substrate
US7824935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2008 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Sep 8, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.