Structure for stochastic integrated circuit personalization
US7838873B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2008 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | May 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.