Semiconductor device having dual metal gates and method of manufacture

US7838908B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Unoh Kwon · Fishkill, US
• Siddarth A. Krishnan · Newark, US
• Takashi Ando · Tuckahoe, US
• Michael P. Chudzik · Beacon, US
• Martin M. Frank · Dobbs Ferry, US
• William K. Henson · Beacon, US
• Rashmi Jha · Wyoming, US
• Yue Liang · San Jose, US
• Vijay Narayanan · New York, US
• Ravikumar Ramachandran · Beacon, US
• Keith Kwong Hon Wong · Wappingers Falls, US

Key dates

• Filing date: Jan 26, 2009
• Grant date: Nov 23, 2010
• Expiry date: Feb 5, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/691
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.