BEOL interconnect structures with improved resistance to stress

US7847402B2 · kind B2 · utility

Assignees

• International Business Machines Corporation · US
• Chartered Semiconductor Manufacturing LTD · SG
• SAMSUNG ELECTRONICS CO., LTD. · KR

Inventors

• Darryl D. Restaino · Modena, US
• Griselda Bonilla · Hopewell Junction, US
• Christos D. Dimitrakopoulos · Baldwin Place, US
• Stephen M. Gates · Ossining, US
• Jae Hak Kim · Daejeon, KR
• Michael Lane · Somers, US
• Xiao Hu Liu · Briarcliff Manor, US
• Son V. Nguyen · Irvine, US
• Thomas M. Shaw · Peekskill, US
• Johnny Widodo · Singapore, SG

Key dates

• Filing date: Feb 20, 2007
• Grant date: Dec 7, 2010
• Expiry date: May 28, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.