Method for detecting, sampling, analyzing, and correcting marginal patterns in integrated circuit manufacturing
US7853920B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2006 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Jan 13, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N2021/95676
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
One embodiment of a method for detecting, sampling, analyzing, and correcting hot spots in an integrated circuit design allows the identification of the weakest patterns within each design layer, the accurate determination of the impact of process drifts upon the patterning performance of the real mask in a real scanner, and the optimum process correction, process monitoring, and RET improvements to optimize integrated circuit device performance and yield. The combination of high speed simulation coupled with massive data collection capability on actual aerial images and/or resist images at the specific patterns of interest provides a complete methodology for optimum RET implementation and process monitoring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.