Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing

US7868375B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Xian Liu · Sunnyvale, US
• Amitay Levi · Cupertino, US
• Alexander Kotov · San Jose, US
• Yuri Tkachev · Sunnyvale, US
• Viktor Markov · Santa Clara, US
• James Yingbo Jia · Fremont, US
• Chien-Sheng Su · Saratoga, US
• Yaw Wen Hu · Cupertino, US

Key dates

• Filing date: Nov 13, 2009
• Grant date: Jan 11, 2011
• Expiry date: Nov 13, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.