Patent · US Active

Method of producing a semiconductor interconnect architecture including generation of metal holes by via mutation

US7875544B2 · kind B2 · utility

1Cited by

9References

7Claims

0Family size

Assignees

Infineon Technologies AG · DE
International Business Machines Corporation · US
UNITED MICROELECTRONICS CORP. · TW

Inventors

Robert C. Wong · Poughkeepsie, US
Ernst Demm · Putnam Valley, US
Pak Leung · Cedar Park, US
Alexander Hirsch · Munich, DE

Key dates

Filing date	Jan 16, 2007
Grant date	Jan 25, 2011
Priority date	—
Expiry date	May 4, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.