Method for transistor fabrication with optimized performance

US7883953B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Da Zhang · New Taipei, TW
• Voon-Yew Thean · Fishkill, US
• Christopher V. Baiocco · Newburgh, US
• Jie Chen · New Taipei, TW
• Weipeng Li · Beacon, US
• Young Way Teh · Singapore, SG
• Jin Z. Wallner · Albany, US

Key dates

• Filing date: Sep 30, 2008
• Grant date: Feb 8, 2011
• Expiry date: Sep 30, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/691

Abstract

A semiconductor process and apparatus includes forming <100> channel orientation CMOS transistors (24, 34) with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer (51) over the PMOS and NMOS gate structures, etching the tensile etch stop layer (51) to form tensile sidewall spacers (62) on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer (72) over the NMOS and PMOS gate structures (26, 36) and the tensile sidewall spacers (62). In other embodiments, a first hydrogen-rich etch stop layer (81) is deposited and etched to form sidewall spacers (92) on the exposed gate sidewalls, and then a second tensile etch stop layer (94) is deposited over the NMOS and PMOS gate structures (26, 36) and the sidewall spacers (92).