Memory cells, electronic systems, methods of forming memory cells, and methods of programming memory cells

US7898850B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Kyu S. Min · San Jose, US
• Rhett T. Brewer · Santa Clara, US
• Tejas Krishnamohan · Palo Alto, US
• Thomas M. Graettinger · Boise, US
• D. V. Nirmal Ramaswamy · Boise, US
• Ronald A. Weimer · Boise, US
• Arup Bhattacharyya · South Burlington, US

Key dates

• Filing date: Oct 12, 2007
• Grant date: Mar 1, 2011
• Expiry date: Dec 2, 2029

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S977/943
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.