Fluorine plasma treatment of high-k gate stack for defect passivation
US7902018B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2007 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | May 8, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28202
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention generally provide a method for forming a dielectric material with reduced bonding defects on a substrate. In one embodiment, the method comprises forming a dielectric layer having a desired thickness on a surface of a substrate, exposing the substrate to a low energy plasma comprising a fluorine source gas to form a fluorinated dielectric layer on the substrate without etching the dielectric layer, and forming a gate electrode on the substrate. In certain embodiments, the fluorine source gas is a carbon free gas. In certain embodiments, the method further comprises co-flowing a gas selected from the group consisting of argon, helium, N2, O2, and combinations thereof with the fluorine source gas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.