Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device

US7906383B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Ralf Richter · Dresden, DE
• Andy Wei · Queensbury, US
• Manfred Horstmann · Dresden, DE
• Joerg Hohage · Dresden, DE

Key dates

• Filing date: Mar 10, 2008
• Grant date: Mar 15, 2011
• Expiry date: Apr 10, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0167

Abstract

By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of transistors by stressed overlayers may be enhanced while nevertheless transistor performance gain may be obtained for each type of transistor, since a highly stressed material positioned above the previously relaxed portion may also efficiently affect the underlying transistor.