Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material
US7915134B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2008 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Jul 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.