Semiconductor chip with solder joint protection ring
US7923850B2 · kind B2 · utility
2Cited by
16References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2008 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Oct 22, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various semiconductor chip arrangements and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip that has an external peripheral wall to a first side of a substrate. A first metallic ring is coupled to the first side of the substrate. The first metallic ring has an internal peripheral wall that frames the semiconductor chip and is separated from the external peripheral wall by a gap. The first metallic ring has a coefficient of thermal expansion less than about 6.0 10−6 K−1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.