Dual metal and dual dielectric integration for metal high-k FETs
US7943457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2009 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Apr 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/66
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.