Wafer level chip scale package and process of manufacture
US7955893B2 · kind B2 · utility
8Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2008 |
| Grant date | Jun 7, 2011 |
| Priority date | — |
| Expiry date | Jul 26, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.