FinFET structures with stress-inducing source/drain-forming spacers and methods for fabricating the same

US7977174B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Scott Luning · San Francisco, US
• Frank Scott Johnson · South San Francisco, US
• Michael Hargrove · Clinton Corners, US

Key dates

• Filing date: Jun 8, 2009
• Grant date: Jul 12, 2011
• Expiry date: Oct 6, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/215

Abstract

Methods for fabricating FinFET structures with stress-inducing source/drain-forming spacers and FinFET structures having such spacers are provided herein. In one embodiment, a method for fabricating a FinFET structure comprises fabricating a plurality of parallel fins overlying a semiconductor substrate. Each of the fins has sidewalls. A gate structure is fabricated overlying a portion of each of the fins. The gate structure has sidewalls and overlies channels within the fins. Stress-inducing sidewall spacers are formed about the sidewalls of the fins and the sidewalls of the gate structure. The stress-inducing sidewall spacers induce a stress within the channels. First conductivity-determining ions are implanted into the fins using the stress-inducing sidewall spacers and the gate structure as an implantation mask to form source and drain regions within the fins.