Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS

US7999325B2 · kind B2 · utility

Assignee

• GlobalFoundries Singapore Pte. Ltd. · SG

Inventors

• Young Way Teh · Singapore, SG
• Yong Meng Lee · Singapore, SG
• Chung Woh Lai · Singapore, SG
• Wenhe Lin · Saratoga Springs, US
• Khee Yong Lim · Singapore, SG
• Wee Leng Tan · Singapore, SG
• John Sudijono · Singapore, SG
• Hui Peng Koh · Singapore, SG
• Liang-Choo Hsia · Singapore, SG

Key dates

• Filing date: Sep 30, 2008
• Grant date: Aug 16, 2011
• Expiry date: Nov 8, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0184

Abstract

An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.