SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable

US8013399B2 · kind B2 · utility

Assignee

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

• Olivier Thomas · Saint-Martin-d'Hères, FR
• Perrine Batude · Dijon, FR
• Arnaud Pouydebasque · Eindhoven, NL
• Maud Vinet · Voiron, FR

Key dates

• Filing date: May 15, 2009
• Grant date: Sep 6, 2011
• Expiry date: May 15, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/00

Abstract

A static random access memory cell which, on a substrate surmounted by a stack of layers, including: a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor are connected to a word line and are arranged between a first bit line and a first storage node and a second bit line and a second storage node, respectively; and a second plurality of transistors forming a flip-flop and situated at least one other level of the stack, beneath said given level, wherein the transistors of the second plurality of transistors each comprising a gate electrode situated opposite a channel region of a transistor of the first plurality of transistors and separated from this channel region by an insulating region provided to enable coupling of said gate electrode and said channel region.