Methods for fabricating non-planar semiconductor devices having stress memory
US8039349B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2009 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Aug 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/796
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of a method are provided for fabricating a non-planar semiconductor device including a substrate having a plurality of raised crystalline structures formed thereon. In one embodiment, the method includes the steps of amorphorizing a portion of each raised crystalline structure included within the plurality of raised crystalline structures, forming a sacrificial strain layer over the plurality of raised crystalline structures to apply stress to the amorphized portion of each raised crystalline structure, annealing the non-planar semiconductor device to recrystallize the amorphized portion of each raised crystalline structure in a stress-memorized state, and removing the sacrificial strain layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.