Closed-loop sputtering controlled to enhance electrical characteristics in deposited layer
US8053364B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2008 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Feb 8, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with metal oxide deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of a desired electrical property as a function of cathode voltage used during a sputtering process that uses a biased target. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials (e.g., metals and oxygen source), be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.