Patent · US Active

Method of testing an integrity of a material layer in a semiconductor structure

US8058081B2 · kind B2 · utility

0Cited by

6References

18Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Moritz Andreas Meyer · Pulheim, DE
Eckhard Langer · Radebeul, DE
Frank Koschinsky · Radebeul, DE

Key dates

Filing date	Jul 13, 2007
Grant date	Nov 15, 2011
Priority date	—
Expiry date	Jan 10, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH01L22/12
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method comprises providing a semiconductor structure. The semiconductor structure comprises a feature comprising a first material and a layer of a second material formed over the feature. The semiconductor structure is exposed to an etchant. The etchant is adapted to selectively remove the first material, leaving the second material substantially intact. After exposing the semiconductor structure to the etchant, it is detected whether the feature has been affected by the etchant.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.