Circuit device with at least partial packaging and method for forming
US8072062B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2008 |
| Grant date | Dec 6, 2011 |
| Priority date | — |
| Expiry date | Jul 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit device is placed within an opening of a conductive layer which is then partially encapsulated with an encapsulant so that the active surface of the circuit device is coplanar with the conductive layer. At least a portion of the conductive layer may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device may be placed on a conductive layer such that an active surface of circuit device is between conductive layer and an opposite surface of circuit device. The conductive layer has at least one opening to expose the active surface of circuit device. The encapsulant may be electrically conductive or electrically non-conductive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.