Method of enhancing on-chip inductance structure utilizing silicon through via technology
US8079134B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2008 |
| Grant date | Dec 20, 2011 |
| Priority date | — |
| Expiry date | Jun 19, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49075
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method is provided that utilizes silicon through via technology, to build a Toroid into the chip with the addition of a layer of magnetic material such as Nickel above and below the T-coil stacked multi-ring structure. This allows the connection between the inner via and an array of outer vias. This material is added on a BEOL metal layer or as an external coating on the finished silicon. Depending on the configuration and material used for the via, the inductance will increase approximately two orders of magnitude (e.g., by utilizing a nickel via core). Moreover, a ferrite material with proper thermal conduction properties is used in one embodiment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.