Calibration technique for measuring gate resistance of power MOS gate device at wafer level
US8174283B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2009 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Feb 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
This invention discloses a method for calibrating a gate resistance measurement of a semiconductor power device that includes a step of forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a resistance and a capacitance of the RC network to prepare for carrying out a wafer-level measurement calibration of the semiconductor power device. The method further includes a step of connecting a probe card to a set of contact pads on the semiconductor wafer for carrying out the wafer-level measurement calibration followed by performing a gate resistance Rg measurement for the semiconductor power chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.