Patent · US Active

Method and apparatus for designing and integrated circuit

US8175737B2 · kind B2 · utility

57Cited by

4References

20Claims

0Family size

Assignees

Freeescale Semiconductor, Inc. · US
KONINKLIJKE PHILIPS ELECTRONICS NV · NL

Inventors

Kevin Lucas · Austin, US
Robert Boone · Grenoble, FR
James E. Vasek · Austin, US
William L. Wilkinson · Schreiber, CA
Christophe Couderc · Marigot, FR

Key dates

Filing date	Jul 19, 2006
Grant date	May 8, 2012
Priority date	—
Expiry date	Feb 15, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG03F1/36
WIPO fieldOptics
WIPO sectorInstruments

Abstract

Method and apparatus for designing an integrated circuit by adding a plurality of control points to an integrated circuit wafer design. Each control point has at least one attribute. Then, an integrated circuit wafer is manufactured using the integrated circuit wafer design. A defect on the integrated circuit wafer is then located. The control points are adjusted such that they correspond with the defect.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.