Stressed Fin-FET devices with low contact resistance

US8207038B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kangguo Cheng · Schenectady, US
• Bruce B. Doris · Brewster, US
• Ali Khakifirooz · Los Altos, US
• Pranita Kulkarni · Slingerlands, US
• Ghavam G. Shahidi · Pound Ridge, US

Key dates

• Filing date: May 24, 2010
• Grant date: Jun 26, 2012
• Expiry date: Oct 23, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6219

Abstract

A method for fabricating an FET device is disclosed. The method includes Fin-FET devices with fins that are composed of a first material, and then merged together by epitaxial deposition of a second material. The fins are vertically recesses using a selective etch. A continuous silicide layer is formed over the increased surface areas of the first material and the second material, leading to smaller resistance. A stress liner overlaying the FET device is afterwards deposited. An FET device is also disclosed, which FET device includes a plurality of Fin-FET devices, the fins of which are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device.