Method of fabricating complementary metal-oxide-semiconductor (CMOS) device
US8211801B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 2, 2010 |
| Grant date | Jul 3, 2012 |
| Priority date | — |
| Expiry date | Jan 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a CMOS device having high-k dielectric layer and metal gate electrode is provided. First, an isolation structure is formed in a substrate to define a first-type and a second-type MOS regions; an interfacial layer and a high-k dielectric layer are sequentially formed over the substrate; a first and a second cover layers are respectively formed over a portion of the high-k dielectric layer at the first-type MOS region and another portion of the high-k dielectric layer at the second-type MOS region; afterwards, an in-situ etching step is performed to sequentially etch the first and second cover layers using a first etching solution and to etch both the high-k dielectric layer and the interfacial layer using a second etching solution until the substrate is exposed. Wherein, the second etching solution is a mixed etching solution containing the first etching solution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.