Chiu-Hsien Yeh
24Patents
4h-index
60Co-inventors
58Inventor score
Filing activity: Sep 21, 2009 → Feb 1, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8232154B2 | Method for fabricating semiconductor device | Electricity | 6 | Active |
| US8426284B2 | Manufacturing method for semiconductor structure | Electricity | 6 | Active |
| US8551876B2 | Manufacturing method for semiconductor device having metal gate | Electricity | 5 | Active |
| US10151048B1 | Manufacturing method of epitaxial contact structure in semiconductor memory device | Electricity | 4 | Active |
| US8987096B2 | Semiconductor process | Electricity | 4 | Active |
| US8405155B2 | Semiconductor structure with gate structure, source/drain region and recess filling with epitaxial layer | Electricity | 4 | Active |
| US9281201B2 | Method of manufacturing semiconductor device having metal gate | Electricity | 4 | Active |
| US9899491B2 | Semiconductor device and method of forming the same | Electricity | 3 | Active |
| US8552503B2 | Strained silicon structure | Electricity | 3 | Active |
| US8329547B2 | Semiconductor process for etching a recess into a substrate by using an etchant that contains hydrogen peroxide | Electricity | 2 | Active |
| US8980753B2 | Metal gate transistor and method for fabricating the same | Electricity | 2 | Active |
| US10026827B2 | Method for fabricating semiconductor device | Electricity | 2 | Active |
| US10290736B2 | Semiconductor device and method of forming the same | Electricity | 1 | Active |
| US9312258B2 | Strained silicon structure | Electricity | 1 | Active |
| US8981527B2 | Resistor and manufacturing method thereof | Electricity | 1 | Active |
| US9685383B2 | Method of forming semiconductor device | Electricity | 1 | Active |
| US8551847B2 | Method for forming metal gate | Electricity | 1 | Active |
| US8211801B2 | Method of fabricating complementary metal-oxide-semiconductor (CMOS) device | Electricity | 0 | Active |
| US8298950B2 | Method of etching sacrificial layer | Electricity | 0 | Active |
| US8404591B2 | Method of fabricating complementary metal-oxide-semiconductor (CMOS) device | Electricity | 0 | Active |
| US10157744B2 | Method for forming patterns of semiconductor device | Electricity | 0 | Active |
| US8252515B2 | Method for removing photoresist | Electricity | 0 | Active |
| US10043882B2 | Method of forming semiconductor device | Electricity | 0 | Active |
| US9000568B2 | Semiconductor structure and fabrication method thereof | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.