Patent · US Active

Memory cells containing charge-trapping zones

US8228743B2 · kind B2 · utility

42Cited by

12References

7Claims

0Family size

Assignee

Micron Technology, Inc. · US

Inventors

Kyu S. Min · San Jose, US
Rhett T. Brewer · Santa Clara, US
Tejas Krishnamohan · Palo Alto, US
Thomas M. Graettinger · Boise, US
D. V. Nirmal Ramaswamy · Boise, US
Ronald A. Weimer · Boise, US
Arup Bhattacharyya · South Burlington, US

Key dates

Filing date	Feb 10, 2011
Grant date	Jul 24, 2012
Priority date	—
Expiry date	Feb 10, 2031

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY10S977/943
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.