Patent · US Active

Shielded gate trench MOSFET device and fabrication

US8236651B2 · kind B2 · utility

14Cited by
8References
18Claims
0Family size

Assignee

Inventors

Key dates

Filing dateAug 14, 2009
Grant dateAug 7, 2012
Priority date—
Expiry dateAug 24, 2030

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/663
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.