Power MOS device fabrication
US8288229B2 · kind B2 · utility
7Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2011 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Mar 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/64
Abstract
Fabricating a semiconductor device includes forming a hard mask on the substrate having a top substrate surface; forming a gate trench in the substrate, through the hard mask; depositing gate material in the gate trench; removing the hard mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; and disposing an anti-punch through implant along at least a section of the trench wall but not along the trench bottom.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.