Patent · US Active

Method for integrating multiple threshold voltage devices for CMOS

US8309447B2 · kind B2 · utility

19Cited by
0References
27Claims
0Family size

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Key dates

Filing dateAug 12, 2010
Grant dateNov 13, 2012
Priority date
Expiry dateOct 22, 2030

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/0188

Abstract

A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.