Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics

US8357610B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Frank Feustel · Dresden, DE
• Thomas Werner · Radebeul, DE
• Michael Grillberger · Radebeul, DE
• Kai Frohberg · Meißen, DE

Key dates

• Filing date: Jan 16, 2009
• Grant date: Jan 22, 2013
• Expiry date: Jul 4, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

By forming a protection layer prior to the application of the planarization layer during a dual damascene strategy for first patterning vias and then trenches, enhanced etch fidelity may be accomplished. In other aspects disclosed herein, via openings and trenches may be patterned in separate steps, which may be accomplished by different etch behaviors of respective dielectric materials and/or the provision of an appropriate etch stop layer, while filling the via opening and the trench with a barrier material and a highly conductive metal may be achieved in a common fill sequence. Hence, the via opening may be formed on the basis of a reduced aspect ratio, while nevertheless providing a highly efficient overall process sequence.