Self-aligned patterned etch stop layers for semiconductor devices
US8367544B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2009 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Feb 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76829
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.