Method and apparatus for designing an integrated circuit using inverse lithography technology
US8370773B2 · kind B2 · utility
3Cited by
24References
19Claims
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Key dates
| Filing date | Aug 16, 2006 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Oct 19, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Method and apparatus for designing an integrated circuit by calculating an optimised reticle layout design from an IC layout design and a model describing an optical system for transferring the IC layout design onto a semiconductor wafer using a reticle, wherein the IC layout design comprises features defined by a plurality of boundaries. Approximating the plurality of boundaries to generate an approximated IC layout design suitable for the manufacture of the IC. Performing OPC simulation on at least a portion of the approximated IC layout design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.