Generation of metal holes by via mutation

US8378493B2 · kind B2 · utility

Assignees

• Infineon Technologies AG · DE
• International Business Machines Corporation · US
• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Robert C. Wong · Poughkeepsie, US
• Ernst Demm · Putnam Valley, US
• Pak Leung · Cedar Park, US
• Alexander Hirsch · Munich, DE

Key dates

• Filing date: Dec 13, 2010
• Grant date: Feb 19, 2013
• Expiry date: Mar 7, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A semiconductor interconnect architecture provides a reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) without degradation of the product yield or robustness, or increases copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.