Finishing method for a silicon on insulator substrate
US8389412B2 · kind B2 · utility
1Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2010 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Mar 17, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/30604
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.