Method of fabricating complementary metal-oxide-semiconductor (CMOS) device
US8404591B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | May 29, 2012 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | May 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a MOS device comprises steps as follows: An interfacial layer, a high-k dielectric layer and a cover layer on a substrate are sequentially formed. Then an in-situ wet etching step is performed by sequentially using a first etching solution to etch the cover layer and using a second etching solution to etch the high-k dielectric layer and the interfacial layer until the substrate is exposed, wherein the second etching solution is a mixed etching solution containing the first etching solution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.