Package-on-package interconnect stiffener

US8513792B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Sanka Ganesan · Chandler, US
• Yosuke Kanaoka · Phoenix, US
• Ram Viswanath · Phoenix, US
• Rajasekaran Swaminathan · Chandler, US
• Robert M. Nickerson · Chandler, US
• Leonel Arana · Phoenix, US
• John S. Guzek · Chandler, US
• Yoshihiro Tomita · Tsukuba, JP

Key dates

• Filing date: Apr 10, 2009
• Grant date: Aug 20, 2013
• Expiry date: Jun 14, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3511
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.