Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions
US8530894B2 · kind B2 · utility
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28References
7Claims
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Key dates
| Filing date | May 18, 2012 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | May 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.