Method of manufacturing a semiconductor device using an etchant
US8557651B2 · kind B2 · utility
2Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2011 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Mar 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an etchant for etching a capping layer having etching selectivity with respect to a dielectric layer, the capping layer changes compositions of the dielectric layer, to thereby control a threshold voltage of a gate electrode including the dielectric layer. The etchant includes about 0.01 to 3 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt and a solvent. Accordingly, the dielectric layer is prevented from being damaged by the etching process for removing the capping layer and the electric characteristics of the gate electrode are improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.