Cut-very-last dual-epi flow
US8569152B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2012 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Jun 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0243
Abstract
A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.