Patent · US Active

Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices

US8569842B2 · kind B2 · utility

73Cited by

8References

30Claims

0Family size

Assignee

Infineon Technologies Austria AG · AT

Inventors

Rolf Weis · Dresden, DE
Franz Hirler · Isen, DE
Matthias Stecher · Munich, DE
Armin Willmeroth · Friedberg, DE
Gerald Deboy · Klagenfurt, AT
Martin Feldtkeller · Munich, DE

Key dates

Filing date	Oct 17, 2011
Grant date	Oct 29, 2013
Priority date	—
Expiry date	Oct 17, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/87
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.