Stacked dual chip package and method of fabrication
US8581376B2 · kind B2 · utility
16Cited by
20References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2010 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Nov 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.