Patent · US Active

Memory scheduler for managing maintenance operations in a resistive memory in response to a trigger condition

US8595449B2 · kind B2 · utility

7Cited by

2References

24Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Michael Kund · Bad Aibling, DE
Thomas Happ · Tarrytown, US
GillYong Lee · Dresden, DE
Heinz Hoenigschmid · Starnberg, DE
Rolf Weis · Dresden, DE
Christoph Ludwig · Radeberg, DE

Key dates

Filing date	Sep 2, 2008
Grant date	Nov 26, 2013
Priority date	—
Expiry date	Mar 16, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG11C16/3431
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.