Spacer-less low-K dielectric processes
US8624329B2 · kind B2 · utility
5Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2009 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Jan 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
Abstract
A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.